1. Field of the Invention
The invention relates to a memory cell for providing an information item having a programmable metallization cell (PMC) resistance component. The invention furthermore relates to a memory circuit having such a memory cell and to a method for producing a memory cell having a PMC resistance component.
2. Description of the Related Art
Semiconductor memory cells based on PMC resistance components are generally known. A PMC resistance component has a solid electrolyte material in which a conductive path can optionally be formed or withdrawn to assume a high-resistance or a low-resistance state that can be assigned to a logic state. Such memory cells based on a PMC resistance component are disclosed, for example, in the following documents: M. N. Kozicki, M. Yun, L. Hilt, A. Singh, Applications Of Programmable Resistance Changes In Metal-Doped Chalcogenides, Electrochemical Society Proc., Vol. 99-13 (1999) 298; R. Neale, Micron To Look Again At Non-Volatile Amorphous Memory, Electronic Engineering Design (2002) and B. Prince, Emerging Memories—Technologies and Trends, Kluwer Academic Publishers (2002).
PMC resistance components usually have a very high ratio of the resistance values of the low-resistance state and the high-resistance state, which is primarily governed by the very high-resistance state of the solid electrolyte material in the unprogrammed state, i.e., when the conductive path is not formed. Typical values for the high-resistance state are greater than 1010 ohms, while typical values for the low-resistance state are approximately 105 ohms (given an active cell area of less than 1 μm2 and an active layer thickness of approximately 50 nm).
For the individual cell, the high resistance ratio between high-resistance and low-resistance state is favorable for the evaluation of the state of the cell. However, in the realization of a memory cell array with evaluation and drive circuits, a number of disadvantages are associated with the above mentioned resistance values. First, the cells can be driven by low switching voltages whose typical values lie in the range of 50 mV to 300 mV. Cells in a cell array which are electrically insulated from a defined electrical potential such as the bit/word or plate lines (e.g., by means of the turned-off selection transistor or the extremely high-value resistance of the cell) are therefore very sensitive to noise which, when coupled in, may lead to inadvertent switching of the cell. Furthermore, application of signals to bit and word lines of the memory cell array, as a result of the capacitive coupling, may give rise to a voltage at the order of magnitude of the switching voltage of the non-selected cells as well. This effect primarily relates to memory cells whose solid electrolyte is in the high-resistance state.
An input of the read-out amplifier which is connected to the memory cell during read-out is usually realized with the aid of an operational amplifier with a feedback resistor. For good discrimination between the low-resistance and high-resistance state, the feedback resistor has to be adapted to the resistance of the cell. High resistance values result in this case and require a large area requirement, particularly when such a memory cell is realized using CMOS technology.
Furthermore, the high resistance values result in high RC time constants and very low current values for the detection of the high-resistance state. Thus, the evaluation of the state can be slowed down significantly.
Moreover, the cells exhibit degradation with regard to the high-resistance state over the service life, particularly under stress conditions, such as in the case of many read-in/read-out operations. This effect is described, for example, in the document R. Symanczyk et al., Electrical Characterization of Solid State Ionic Memory Elements, Proceedings Non-Volatile Memory Technology Symposium (2003). The degradation is manifested in a reduction of the resistance value in the high-resistance state and signifies an undesirable inhomogeneity of the cell properties in a memory cell array.